Development and evaluation of haltere-mimicking gyroscope for three-axis angular velocity sensing using a haltere-mimicking structure pair.

This paper presents a three-axis biomimetic gyroscope, mimicking the haltere of Diptera. Diptera use a club-shaped mechanosensory organ called the haltere to get the three-axis angular velocity information, namely roll, pitch and yaw axes, for flight control. One pair of halteres is physically connected to the wings of Diptera that vibrate in antiphase to the flapping wings in ambient air. They sense the Coriolis force and relay angular velocity information to the Diptera. As an alternative to the conventional micro-electro-mechanical system gyroscopes which are widely used in robotics, many research groups have attempted to mimic the haltere. However, no previous study succeeded in measuring all three-axis components of angular velocity, due to various shortcomings. In this paper, we developed the first three-axis haltere-mimicking gyroscope. Two perpendicularly positioned haltere-mimicking structures that can vibrate at a 180° amplitude were mechanically integrated into a robot actuator. Two accelerometers, placed at the tip of each structure, were employed to measure the Coriolis force. The performance of the novel biomimetic gyroscope was measured in all rotational directions, using a motion capture system as the ground truth. One-axis input experiments were performed 240 times at different input magnitudes and directions, and the measured orientation error was less than ±2.0% in all experiments. In 80 three-axis input experiments, the orientation error was less than ±3.5%.

Implementation of Flip-Chip Microbump Bonding between InP and SiC Substrates for Millimeter-Wave Applications.

Flip-chip microbump (µ-bump) bonding technology between indium phosphide (InP) and silicon carbide (SiC) substrates for a millimeter-wave (mmW) wireless communication application is demonstrated. The proposed process of flip-chip µ-bump bonding to achieve high-yield performance utilizes a SiO2-based dielectric passivation process, a sputtering-based pad metallization process, an electroplating (EP) bump process enabling a flat-top µ-bump shape, a dicing process without the peeling of the dielectric layer, and a SnAg-to-Au solder bonding process. By using the bonding process, 10 mm long InP-to-SiC coplanar waveguide (CPW) lines with 10 daisy chains interconnected with a hundred µ-bumps are fabricated. All twelve InP-to-SiC CPW lines placed on two samples, one of which has an area of approximately 11 × 10 mm2, show uniform performance with insertion loss deviation within ±10% along with an average insertion loss of 0.25 dB/mm, while achieving return losses of more than 15 dB at a frequency of 30 GHz, which are comparable to insertion loss values of previously reported conventional CPW lines. In addition, an InP-to-SiC resonant tunneling diode device is fabricated for the first time and its DC and RF characteristics are investigated.

Artificial Compound Eye Systems and Their Application: A Review.

The natural compound eye system has many outstanding properties, such as a more compact size, wider-angle view, better capacity to detect moving objects, and higher sensitivity to light intensity, compared to that of a single-aperture vision system. Thanks to the development of micro- and nano-fabrication techniques, many artificial compound eye imaging systems have been studied and fabricated to inherit fascinating optical features of the natural compound eye. This paper provides a review of artificial compound eye imaging systems. This review begins by introducing the principle of the natural compound eye, and then, the analysis of two types of artificial compound eye systems. We equally present the applications of the artificial compound eye imaging systems. Finally, we suggest our outlooks about the artificial compound eye imaging system.

A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 µm CMOS Technology.

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect's movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 µm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

Reconfigurable Sensor Analog Front-End Using Low-Noise Chopper-Stabilized Delta-Sigma Capacitance-to-Digital Converter.

This paper proposes a reconfigurable sensor analog front-end using low-noise chopper-stabilized delta-sigma capacitance-to-digital converter (CDC) for capacitive microsensors. The proposed reconfigurable sensor analog front-end can drive both capacitive microsensors and voltage signals by direct conversion without a front-end amplifier. The reconfigurable scheme of the front-end can be implemented in various multi-mode applications, where it is equipped with a fully integrated temperature sensor. A chopper stabilization technique is implemented here to achieve a low-noise characteristic by reducing unexpected low-frequency noises such as offsets and flicker noise. The prototype chip of the proposed sensor analog front-end is fabricated by a standard 0.18-µm 1-poly-6-metal (1P6M) complementary metal-oxide-semiconductor (CMOS) process. It occupies a total active area of 5.37 mm² and achieves an effective resolution of 16.3-bit. The total power consumption is 0.843 mW with a 1.8 V power supply.

Characterization of the Piezoresistive Effects of Silicon Nanowires.

Silicon nanowires (SiNWs) have received attention in recent years due to their anomalous piezoresistive (PZR) effects. Although the PZR effects of SiNWs have been extensively researched, they are still not fully understood. Herein, we develop a new model of the PZR effects of SiNWs to characterize the PZR effects. First, the resistance of SiNW is modeled based on the surface charge density. The characteristics of SiNW, such as surface charge and effective conducting area, can be estimated by using this resistance model. Then, PZR effects are modeled based on stress concentration and piezopinch effects. Stress concentration as a function of the physical geometry of SiNWs can amplify PZR effects by an order of magnitude. The piezopinch effects can also result in increased PZR effects that are at least two times greater than that of bulk silicon. Experimental results show that the proposed model can predict the PZR effects of SiNWs accurately.

0.6 V, 116 nW Neural Spike Acquisition IC with Self-Biased Instrumentation Amplifier and Analog Spike Extraction.

This paper presents an ultralow power 0.6 V 116 nW neural spike acquisition integrated circuit with analog spike extraction. To reduce power consumption, an ultralow power self-biased current-balanced instrumentation amplifier (IA) is proposed. The passive RC lowpass filter in the amplifier acts as both DC servo loop and self-bias circuit. The spike detector, based on an analog nonlinear energy operator consisting of a low-voltage open-loop differentiator and an open-loop gate-bulk input multiplier, is designed to emphasize the high frequency spike components nonlinearly. To reduce the spike detection error, the adjacent spike merger is also proposed. The proposed circuit achieves a low IA current consumption of 46.4 nA at 0.6 V, noise efficiency factor (NEF) of 1.81, the bandwidth from 102 Hz to 1.94 kHz, the input referred noise of 9.37 µVrms, and overall power consumption of 116 nW at 0.6 V. The proposed circuit can be used in the ultralow power spike pulses acquisition applications, including the neurofeedback systems on peripheral nerves with low neuron density.

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

BACKGROUND: Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. OBJECTIVE: This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. METHODS: Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). RESULTS: The proposed IC is fabricated by using a standard 0.18 µm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 µA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 µVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. CONCLUSIONS: The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

Reconfigurable Multiparameter Biosignal Acquisition SoC for Low Power Wearable Platform.

A low power and low noise reconfigurable analog front-end (AFE) system on a chip (SoC) for biosignal acquisition is presented. The presented AFE can be reconfigured for use in electropotential, bioimpedance, electrochemical, and photoelectrical modes. The advanced healthcare services based on multiparameter physiological biosignals can be easily implemented with these multimodal and highly reconfigurable features of the proposed system. The reconfigurable gain and input referred noise of the core instrumentation amplifier block are 25 dB to 52 dB, and 1 µVRMS, respectively. The power consumption of the analog blocks in one readout channel is less than 52 µW. The reconfigurable capability among various modes of applications including electrocardiogram, blood glucose concentration, respiration, and photoplethysmography are shown experimentally.

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 µW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Biopotential Acquisition Analog Front-End IC.

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

Analog front-end measuring biopotential signal with effective offset rejection loop.

This paper presents an analog front-end (AFE) IC design for recording biopotential signals. The AFE employs a capacitively coupled instrumentation amplifier to achieve a low-noise and high-common mode rejection ratio (CMRR) system. A ripple reduction loop is proposed to reduce the ripple generated by the up-modulating chopper. The low frequency noise is attenuated by an input AC coupling capacitor, and is attenuated again by a DC servo loop. The proposed AFE features a differential gain of 71 dB, and a CMRR of 89 dB, at 50 Hz. Furthermore, the proposed AFE can robustly acquire biopotential signals even in the presence of an input offset and ripples.

Light-controlled biphasic current stimulator IC using CMOS image sensors for high-resolution retinal prosthesis and in vitro experimental results with rd1 mouse.

Retinal prosthetic devices stimulate retinal nerve cells with electrical signals proportional to the incident light intensities. For a high-resolution retinal prosthesis, it is necessary to reduce the size of the stimulator pixels as much as possible, because the retinal nerve cells are concentrated in a small area of approximately 5 mm × 5 mm. In this paper, a miniaturized biphasic current stimulator integrated circuit is developed for subretinal stimulation and tested in vitro. The stimulator pixel is miniaturized by using a complementary metal-oxide-semiconductor (CMOS) image sensor composed of three transistors. Compared to a pixel that uses a four-transistor CMOS image sensor, this new design reduces the pixel size by 8.3%. The pixel size is further reduced by simplifying the stimulation-current generating circuit, which provides a 43.9% size reduction when compared to the design reported to be the most advanced version to date for subretinal stimulation. The proposed design is fabricated using a 0.35 µm bipolar-CMOS-DMOS process. Each pixel is designed to fit in a 50 µ m × 55 µm area, which theoretically allows implementing more than 5000 pixels in the 5 mm × 5 mm area. Experimental results show that a biphasic current in the range of 0 to 300 µA at 12 V can be generated as a function of incident light intensities. Results from in vitro experiments with rd1 mice indicate that the proposed method can be effectively used for retinal prosthesis with a high resolution.

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-µm complementary metal-oxide-semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 µA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 µW and has an input referred current noise of 260 pArms.

Ambient light cancellation in photoplethysmogram application using alternating sampling and charge redistribution technique.

To overcome a large DC offset, ambient light interference, and optical path variation, a robust PPG readout chip is fabricated using 0.13-µm CMOS process. Against the large DC offset, a saturation detection and current feedback method can compensate a current of up to 30 µA. To be robust against optical path variation, an automatic emitting light compensation method is adopted. To remove the ambient light interference, we propose an alternating sampling and charge redistribution technique, in which no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26 µW and has a input referred current noise of 260 pArms.

Current stimulator IC with adaptive supply regulator for visual prostheses.

The current stimulation method is preferred over the voltage stimulation method in the visual prostheses based on functional electrical stimulation (FES) due to its accurate charge control property. Previous current stimulators are generally implemented using a static high supply voltage, because current stimulations require high output voltage compliance. This high static supply voltage, however, may harm the tissues or damage the electrodes. This paper proposes a novel integrated circuit (IC) current stimulator with adaptive supply regulator (ASR). In the proposed circuit, the internal power supply voltage is not static, but adaptively regulated to the minimum required voltage for stimulation. The current feedback loop in the ASR adaptively increases the internal supply voltage when the monitored current is smaller than the desired current, and reduces the internal supply voltage when the monitored current is higher than the desired current. With this method, the internal supply voltage of the stimulator is minimized, and potential damages of the tissues due to high voltage (HV) stimulation can be reduced. Also the current feedback loop in ASR enhances the accuracy of the output current and the robustness to the load impedance. The stimulator IC is fabricated using 0.35 micro m bipolar-CMOS-DMOS (BCDMOS) process, and the size of the chip is 2000 micro m by 1500 micro m.

Multi-channel stimulator IC using a channel sharing method for retinal prostheses.

A retinal stimulator is an implantable device restoring vision by supplying a controlled, stimulating electrical signal to people blinded by retinal diseases such as age-related macular degeneration (AMD) and retinitis pigmentosa (RP). The resolution requirements of artificial retina systems become increasingly significant in their design as well as their usefulness. At least 32 x 32 pixels are required to provide a minimal visual function. However, a retinal stimulator with a high resolution imposes severe constraints on interface electronics. In this paper, a new stimulator IC (integrated chip) using a channel sharing technique is developed to minimize the circuit size, power consumption, as well as overheating of retina tissues. The proposed current-mode stimulator is fabricated by a 0.35 microm 2-poly/4-metal BCDMOS technology. Attention is given to minimizing the silicon area so that higher channel numbers can be implemented. The stimulator for each channel can provide output current in the range of 0-350 muA. The effective chip area excluding the pads is 1.2 mm x 1.2 mm.

Optimal and robust design method for two-chip out-of-plane microaccelerometers.

In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g∼389 mV/g, the output nonlinearity of 0.43% FSO∼0.60% FSO, the input range of ±2 g and a bias instability of 122 µg∼229 µg. The signal-to-noise ratio and the noise equivalent resolution are measured to be 74.00 dB∼75.23 dB and 180 µg/rtHz∼190 µg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%∼1.9% and 0.3%∼0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.